In the wafer probe tests of semiconductor wafers, including integrated circuits formed on the semiconductor wafers, probe cards are used. The probe cards provide an electrical coupling between a tester or probe station and the semiconductor wafer being probed. The integrated circuits are provided as a plurality of integrated circuit devices (often referred to as “dice” or “bars”) on a planar semiconductor wafer.
The signals that provide power, ground, and input and output signals are electrically coupled to bond pads that are the electrical terminals for the integrated circuit. Because full operational tests and packaging processes for each integrated circuit are very expensive, probe testing is used to verify functionality of the integrated circuit devices and to identify the bad devices prior to the step of singulation. In singulation, the wafer is sawed or separated by laser cutting, mechanical sawing or other means into a plurality of integrated circuit dice. The probe tests provide a method to ensure that only functional devices are processed further. After the singulation process, the ICs are packaged into dual inline packages (DIPs), ball grid array (BGA) and micro-BGA packages, stacked packages, and the like. Because the packaging materials and process steps are quite expensive, tests at probe stations are used to prevent bad devices from being processed further.
Many types of integrated circuits are formed on semiconductor wafers and are subjected to probe testing. For example, programmable logic devices (PLDs) including field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs), memory devices including DRAMs and SRAMs, non-volatile devices such as FLASH and EEPROMs, processors including digital signal processors and microprocessors are all formed as integrated circuits on semiconductor wafers and all of these devices may be subjected to wafer probe testing.
Probe cards are used with probe test stations. The probe card provides a means to engage probes with the lands or bond pads of the integrated circuits while they are still physically together on the semiconductor wafer. The probe pin tips are maintained in a precise alignment pattern with the lands or pads on the wafer. The probes are flexible and may be slightly mechanically compressed, that is, they are designed to have a spring function. This is important so the probes can be aligned with the probe points on the wafer and then brought gently into electrical and physical contact with the corresponding bond pad or ball land. The tester can then apply power and ground to one or more of the integrated circuit dice. By inputting signals into the input pins, providing power and ground signals to the appropriate pins, and capturing signals from the output pins, the wafer probe test may exercise one or more of the integrated circuit dice while it is still part of the wafer, thus verifying that it is a functional device.
Various probe card designs are known in the art. Vertical probe cards provide a generally vertical arrangement of the probe pins on an array of probes. These cards may probe one, two, or many integrated circuit dice in parallel. Many hundreds or even thousands of probes may be used. Probe cards of this type are described, for example, by U.S. Pat. No. 7,535,239, entitled “Probe Card Configured for Interchangeable Heads”, issued May 19, 2009, having common inventorship and co-ownership with the present application, which is hereby incorporated in its entirety herein.
Other probe card arrangements are also used in the semiconductor manufacturing field, including horizontal, cantilever, membrane, spring probes, buckling beam probes, and others known to those skilled in the art.
In order to limit the number of probes and probe pins needed on a probe card to a reasonable number, probe cards are designed with certain techniques. One known technique is to identify repeated pins or bond pads on the IC that are coupled to a power supply, and to probe only a few of these pads. The wafer probe tip may damage the surface of the bond pads that are probed so there is an advantage to not probing every pad. Further, the power pads (Vdd, Vss, Ground) are coupled electrically inside the integrated circuit in parallel, and so it is possible to test the integrated circuit without probing all of these pads. The wafer test probe station need only provide sufficient power and ground connections to operate the integrated circuit for testing.
However, problems with the probe pins of the prior art probe cards sometimes occur. When a power signal or ground signal is probed in this manner, the current flowing through the tip of the probe may spike on certain events. These current spikes, when repeated over many test cycles, may cause the probe tip to “burn”. Probe cards are expensive and so are intended to be repeatedly used to test many wafers. The probe pins should remain uniform in shape and have uniform contact resistance so that consistent test results are obtained for each wafer probed. If this is not the case, then the test results may falsely indicate a device is not functional, or other problems with testing may occur. A burned probe tip has experienced thermal stress due to over current. This burn damage can affect its operation by changing the shape and the contact resistance of the probe tip.
Presently, known probe pins are typically rated for 75-100 milliamperes of current. The probe pins for a prior art probe card are uniform in size; typically, the probe pins are about 3 mils in diameter. However and particularly when a limited number of probe pins are used to probe a power signal, or other high current signal, over time the probe pin may become misshapen and contact resistance may increase. This probe pin damage then requires repair of the probe card, increasing test time and costs. If a repair is not made, the probe card may not perform correctly.
FIG. 1 depicts a prior art probe card 10 arranged as a vertical probe card. In FIG. 1, a substrate 11 is provided. Substrate 11 is typically a printed circuit board (PCB) and has traces and vias that are formed (not shown) to make electrical connections to the probe pins on the probe card. A multiple layer organic (MLO) or multiple layer ceramic (MLC) portion 13 is provided and supports electrically conductive pads or lands 19. The pads are a good conductor material, typically gold or gold alloys, although copper, palladium, palladium plated nickel, nickel plated over copper, copper, copper alloys and copper nickel layers, and other known conductive pad materials may also be used. Substrate 11 includes conductors and vias to provide electrical connections between the probe pins 17 and a wafer probe tester (not shown) for use in powering and testing the device being probed. Typically, probe cards 10 are used to probe wafers with integrated circuit devices fabricated on them, but they could also be used to test packaged integrated circuit devices, circuit boards, thin film circuits, printed circuits, membranes with conductors formed on them and other devices as well.
Probe pins 17 are each coupled to a corresponding one of these pads 19. Probe head 15 is formed to provide mechanical support and to ensure the alignment of the probe pins 17. Probe head 15 is made of, for example, a ceramic housing with holes provided on top and bottom of the housing, a top guide plate and a bottom guide plate, and a thin Mylar in the middle of the head. The probe head thickness is about 4.0-4.5 millimeters but could be more or less than this thickness. The probe head 15 provides physical support and alignment of the probe pins 17. The free end of probes 17, such as end 18, is then available to be placed into physical and electrical contact with a semiconductor wafer. In the prior art probe card 10 of FIG. 1, each probe tip 17 is of uniform diameter and therefore uniform current carrying capacity. The probe card 10 is brought into physical and electrical contact with the wafer under test and each probe tip 17 touches down on a corresponding bond pad or ball land of the integrated circuit(s) on the wafer. Some probe cards test one integrated circuit on the wafer in a “step and repeat” fashion, while others may test multiple integrated circuit devices in parallel by having probe pins mapped to multiple integrated circuit devices. A unique probe card 10 may be designed for each type of wafer to be tested. Alternatively, for example, for commodity type devices such as DRAMs, the pad layout for the integrated circuit dies and the wafer may be made common so that a standardized probe card may be used with a variety of wafers having a common pad layout. More typically, a specific probe card is designed for each type of wafer to be produced as the universal probe cards have not been as practical.
A continuing need thus exists for a probe card that provides reliable wafer probe testing over a lengthy period of time without burning the probe pins and without the need for replacing certain pins due to over current situations.